| A 3 Gb_s multichannel transceiver in 65 nm CMOS technology |
| 张锋;邱玉松; |
| 关键词：transceiver;process variation;low latenc |
| 主要内容：This paper describes a 65 nm 16-bit parallel transceiver IP macro, whose rate is 3 Gb/s with a 5 p F load including the |
| 《Journal of Semiconductors》 2015,36(01):154-161 |
| 全文下载请进入http://hightech.stlib.cn/tpi_1/sysasp/include/index.asp |
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