| A 0.1–1.5 GHz, low jitter, area efficient PLL in 55-nm CMOS process |
| 钟波;朱樟明; |
| 关键词：phase lock loop;freqency synthesizer;dua |
| 主要内容：A 0.1–1.5 GHz, 3.07 pS root mean squares(RMS) jitter, area efficient phase locked loop(PLL) with multiphase clock output |
| 《Journal of Semiconductors》 2016,37(05):94-100 |
| 全文下载请进入http://hightech.stlib.cn/tpi_1/sysasp/include/index.asp |
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